THE TYR FAMILY OF COMPANION PLATFORMS
MAKES INTEGRATION EASY AND
HANDLES ALL TYPES OF ALGORITHMS
2 PETAOPS / 50 W
COMPUTING FOR THE VEHICLE
Handling The Power Gap
Most discussions tend to shy away from examining or even mentioning the effective compute power. This represents the percentage of the nominal gross compute power that can be used at any given instance, and it is algorithm dependent. For example, if a one PetaFlops processor can only deliver 20% of that nominal power at any given instance, its effective compute power would be 200TFlops.
Effective compute power becomes critical in L4/L5 systems, as the total processing power requirement is massive. It impacts the system cost in multiple ways – power consumption, silicon cost, PCB area, cooling provisions, etc. In addition, the effective compute power must be delivered within a very restrictive timing budget, typically less than 25 ms.
The Tyr family of chips was designed around the VSORA scalable, multi-core architecture and integrates ISO26262 / ASIL-B/D functional safety elements such as lockstep. The result is a solution that lends itself just as easily to easy integration in existing systems as to completely new, radical designs. Tyr is fully re-programmable making over-the-air updates simple.
The family is algorithm and host processor agnostic and is capable of handling virtually any algorithm with near theory usable efficiency. New algorithms like Transformers and BEVformer are fully supported and everything is developed using high-level language, which means that it is easy and fast, but also guarantees that anything that can be expressed in this high-level language will run on any of the chips in the family.
Having developed your code aiming at the Tyr 3 and finding it is too powerful for the application is not an issue. Run the code on the Tyr1 or Tyr2 without any issues and at the same time save both power and money!
NEXT GENERATION AI/DSP PLATFORM
Fully programmable companion chip family for Autonomous Driving / Edge Intelligence.
- Algorithm and host processor agnostic
- Straightforward integration in existing s/w & h/w architecture
- Software oriented design flow
AI & DSP on same chip, sharing high b/w on-chip memory
- Minimizes latency and power consumption
- Increases flexibility
- High-level programming throughout
- Supports Software Defined Vehicle
- Handles next generation algorithms like Federated Learning and BEVformer
Very high performance
- 20+ TOPS/W
- Close to theory implementation efficiency
IEEE754 floating point
- fp8 for AI / fp24 for DSP
ISO26262 / ASIL-D ready
- <10W (Tyr1) – <50W (Tyr3)
- 260 Tflops processing power
- 516 Tflops using sparsity
- AI: 65,536 MACs
- DSP: 1,024 ALUs
- 520 Tflops processing power
- 1,032 Tflops using sparsity
- AI: 131,072 MACs
- DSP: 2,048 ALUs
- 1,040 Tflops processing power
- 2,064 Tflops using sparsity
- AI: 262,144 MACs
- DSP: 4,096 ALUs
We would love to tell you more about our Tyr family and how this can be of benefit to you.
Send us a mail to firstname.lastname@example.org
We will take it from there