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Tyr - Autonomous Driving Companion Chips

Never before have this type of power/performance combination been available

DOGMa applications are no longer a dream - Tyr3 will provide <5msec latency for an 8M particle filter (16M particles)

Porting existing code is straightforward - everything is done using high-level language

No need to be forced to use multiple devices or boards, special accelerator solutions, special cooling solutions,...

AND it is small, so it costs less than you expect and consúmes much less than you think!

Introducing Tyr

Introducing Tyr

Since all processing is done using floating point the processing power is shown as Tflops. It is worth noting that fp8 provides better performance than Int8 for AI applications and at the same time consumes less power. Tyr is initially offered in 3 different configuartions:

Tyr1 - 260 Tflops through the use of 64k MACs for AI and 1,024 ALUs for DSP applications

Tyr2 - 520 Tflops through the use of 128k MACs for AI and 2,048 ALUs for DSP applications

Tyr3 - 1,040 Tflops through the use of 256k MACs for AI and 4,096 ALUs for DSP applications

The Tyr family provides an algorithm and host-processor agnostic high performance solution to offload the heavy AI and signal processing requirements from the system main processor. Straightforward, rapid and easy implementation and proved design environment radically simplifies transitioning from L2 to L5.

ISO26262 support is integrated and lockstep solutions can be integrated without adding extra devices.

DOGMa type of applications are supported with superior performance. For example, an 8M particle filter using 16M particles runs with a latency of sub-5 msec on the Tyr3 and sub-10ms on the Tyr2.

Handling The Power Gap

There is an element that studiously is being avoided when discussing full autonomy (L4/L5) for vehicles. It is the effective compute power required when implementing the enormously complex algorithms that are required to execute in real time. The realistic timing budget can be measured in a few tens of milliseconds.

The Tyr family of chips was designed around the VSORA scalable, multi-core architecture used in the AD1028. The result was a solution that lends itself just as easily to easy integration in existing systems as to completely new, radical designs. Tyr is fully re-programmable so over-the-air updates are made simple.

The family is algorithm and host processor agnostic and is capable of handling virtually any algorithm with near theory usable efficiency. Everything is developed using high-level language, which means that it is easy and fast, but also guarantees that anything that can be expressed in this high-level language will run on any of the chips in the family.

Having developed your code aiming at the Tyr 3 and finding it is too powerful for the application is not an issue. Run the code on the Tyr1 or Tyr2 without any issues and at the same time save both power and money!

The Power Gap


Tell Me More About Tyr!

Send a mail to info@vsora.com and we will send you more information.